Task: Verilog Parser

Goal

To build a parser for Verilog. This will allow us to import standard commerical and open source circuit descriptions into PreVIEW, as well as allow us to build simulators and analysis tools for Verilog. It will also allow us to explore extensions to Verilog.

Proposed Work Plan

1. Design and implement an OCaml algebraic datatype to represent the abstract syntax tree (AST) Verilog programs
2. Design and implement a lexer for Verilog. This lexer will read from a file or string and generate a sequence of tokens
3. Implement a parser which will take the sequence of tokens and generate the correct Verilog AST for the circuit.
4. Implement a pretty-printer for the Verilog AST.
5. Implement a translator which will convert PreVIEW programs into equivalent Verilog programs.
6. Implement a translator which will convert Verilog programs into equivalent PreVIEW programs.

Parts 1, 2, and 3 constitute the basic components for representing, reading and writing Verilog programs. Parts 4 and 5 constitute the integration of the parser into PreVIEW.

Tools

The programming language that will be used is OCaml. OCamlLex and OCamlYacc should be used to generate the parser.

Background material, references, and resources

• The Verilog BNF can be found at: http://www.verilog.com/VerilogBNF.html
• Documentation for OCaml can be found online at http://caml.inria.fr/pub/docs/manual-ocaml/index.html and the standard library documentation at http://caml.inria.fr/pub/docs/manual-ocaml/libref/index.html.
• Documentation for OCamlLex and OCamlYacc can be found online as well as in the "Little Rapster"
• The lint project contains a parser and printer for very simple syntax. Turtle and PreVIEW contain a parser and printer for slightly more complicated syntaxes.
• PreVIEW documentation can be found in Ellner's master's thesis and implementation specific documentation can be found by sending me an email or in the PreVIEW source tree under CVS.